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this is a summary document only. a complete document is not avail- able at this time. for more information, please contact your local atmel sales office. 5360as?bdc?0 8 /04 features up to 2 gsps sampling rate power consumption: 4.6w 500 mvpp differential 100 ? or single-ended 50 ? ( 2 %) analog inputs differential 100 ? or single-ended 50 ? clock inputs ecl or lvds output compatibility 50 ? differential outputs with common mode not dependent on temperature adc gain adjust sampling delay adjust offset control capability data ready output with asynchronous reset out-of-range output bit selectable decimation by 32-function gray or binary selectable output data; nrz output mode pattern generator outp ut (for acquisition system monitoring) radiation tolerance oriented design (more than 100 krad (si) expected) ci-cga152 cavity down hermetic package cbga 152 package evaluation board tsev83102g0bgl companion device: dmux 8-/10- bit 1:4/1:8 2 gsps ts81102g0 performance 3.3 ghz full power input bandwidth (-3 db) gain flatness: 0.2 db (from dc up to 1.5 ghz) low input vswr: 1.2 max from dc to 2.5 ghz sfdr = -59 dbc; 7.6 effective bits at f s = 1.4 gsps, f in = 700 mhz [-1 dbfs] sfdr = -53 dbc; 7.1 effective bits at fs = 1.4 gsps, f in = 1950 mhz [-1 dbfs] sfdr = -54 dbc; 6.5 effective bits at f s = 2 gsps, f in = 2 ghz [-1 dbfs] low bit error rate (10 -12 ) at 2 gsps application direct rf down conversion wide band satellite receiver high-speed instrumentation high-speed acquisition systems high-energy physics automatic test equipment radar screening temperature range for packaged device: ? ?m? grade: -40 c < t c ; t j < 125 c standard die flow (upon request) description the TS83102G0BMGS is a monolithic 10-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 2 gsps. it uses an innovative architecture, including an on-chip sample and hold (s/h). the 3.3 ghz full power input bandwidth and band flatness performances enable the digitiz- ing of high if and large bandwidth signals. 10-bit 2 gsps adc mil TS83102G0BMGS summary for more information, please contact hotline-bdc@gfo.atmel.com
2 TS83102G0BMGS 5360as?bdc?0 8 /04 figure 1. simplified block diagram functional description the TS83102G0BMGS is a 10-bit 2 gsps adc. the device includes a front-end master/slave track and hold stage (sample and hold), followed by an analog encoding stage (analog quantizer), which outputs analog residues re sulting from analog quantization. successive banks of latches regenerate the analog residues into logical levels before entering an error correction circuit and resynchronization stage, followed by 50 ? differential output buffers. the TS83102G0BMGS works in a fully differential mode from analog inputs to digital outputs. a differential data ready output (dr/drb) is av ailable to indicate when the outputs are valid and an asynchronous data ready reset ensures that the first digitized data corresponds to the first acquisition. the control pin b/gb (a11 of the ci-cga package) is provided to select either a binary or gray data output format. the gain control pin ga (r9 of the ci-cga package) is provided to adjust the adc gain transfer function. a sampling delay adjust function (sda) may be used to ease the interleaving of adcs. a pattern generator is integrated on the chip for debug or acquisition setup. this function is activated through the pgeb pin (a9 of the ci-cga package). an out-of-range bit (or/orb) indicates when the input overrides 0.5 vpp. a selectable decimation by 32 functions is al so available for enhanced testability coverage (a10 of the ci-cga package), along with the die junction temperature monitoring function. the TS83102G0BMGS uses only vertical isolated npn transistors together with oxide isolated polysilicon resistors, which provides enhanced radiation tolerance (over 100 krad (si) total dose expected tolerance). sample &hold clock generation logic block analog quantizer vin vinb cl k clk b pgeb b/gb drrb or orb d9 d9b d0 d0b ga dr drb 50 50 50 50 sda sda decb/ diode
3 TS83102G0BMGS 5360as?bdc?0 8 /04 TS83102G0BMGS package description table 1. pin description (ci-cga 152) symbol pin number function power supplies v cc , v ccth k1, k2, j3, k3, b6, c6, a7, b7, c7, p8, q8, r8 5v analog supply (connected to same power supply plane) gnd b1, c1, d1, g1, m1, q1, b2, c2, d2, e2, f2, g2, n2, p2, q2, a3, b3, d3, e3, f3, g3, n3, p4, q4, r4, a5, p5, q5, p6, q6, p7, q7, r7, b9, b10, b11, r11, p12, a14, b14, c14, g14, k14, p14, q14, r14, b15, q15, b16, q16 analog ground v ee , v eeth h1, j1, l1, h2, j2, l2, m2, c3, h3, l3, m3, p3, q3, r3, a4, b4, c4, b5, c5, a8, b8, c8, c9, p9, q9, c10, q10, r10 -5v analog supply (connected to same power supply plane) v plusd p10, c11, p11, q11, a12, b12, c12, q12, r12, d14, e14, f14, l14, m14, n14 digital positive supply dv ee a13, b13, c13, p13, q13, r13, h14, j14 -5v digital supply analog inputs vin r5 in-phase (+) analog input signal of the differential sample & hold preamplifier vinb r6 inverted phase (-) analog inpu t signal of the differential sample & hold preamplifier clock inputs clk e1 in-phase (+) clock input clkb f1 inverted phase (-) clock input digital outputs d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 d16, e16, f16, g16, j16, k16, l16, m16, n16, p16 in-phase (+) digital outputs d0 is the lsb, d7 is the msb d0b, d1b, d2b, d3b, d4b, d5b, d6b, d7b, d8b, d9b d15, e15, f15, g15, j15, k15, l15, m15, n15, p15 inverted phase (-) digital outputs or c16 in-phase (+) out-of-range output orb c15 inverted phase (-) out-of-range output dr h16 in-phase (+) data ready signal output drb h15 inverted phase (-) data ready signal output additional functions b/gb a11 binary or gray select output format control - binary output format if b/gb is floating or connected to gnd - gray output format if b/gb is connected to v ee
4 TS83102G0BMGS 5360as?bdc?0 8/ 04 symbol pin number function decb/diode a10 decimation function enable or die junction temperature measurement: - decimation active when low (die junction temperature monitoring is not possible) - normal mode when high or left floating - die junction temperature monitoring when current is applied pgeb a9 active low pattern generator enable - digitized input delivered at outputs according to b/gb if pgeb is floating or connected to gnd - checker board pattern delivered at outputs if pgeb is connected to v ee drrb n1 asynchronous data ready reset function (active at ecl low level) ga r9 gain adjust sda a6 sampling delay adjust sdaen p1 sampling delay adjust enable - inactive if floating or connected to gnd - active if connected to v ee table 1. pin description (ci-cga 152) (continued)
5 TS83102G0BMGS 5360as?bdc?0 8 /04 figure 2. pinout notes: 1. to simplify pcb routing, the 4 nc colu mns can be electrically connected to the gnd columns. 2. the pinout is shown from the bottom. the colu mns and rows are defined differently from the jedec standard. TS83102G0BMGS ci-cga 152 bottom view decb/ diode pgeb orb or
6 TS83102G0BMGS 5360as?bdc?0 8 /04 thermal and moistu re characteristics dissipation by conduction and convection the thermal resistance from junction to ambient rth ja is around 30 c/w. therefore, to lower rth ja , it is mandatory to use an external heat sink to improve dissipation by convection and conduction. the heat sink should be fixed in contact with the top side of the package (ai203 electrical isolation over cuw heat spreader). the heat sink does not need to be electrically isolated, because the top of the package is already electrically isolated thanks to a 0.30 mm ai203 layer. example: the thermal resistance from case to ambient rth ca is typically 4.0 c/w (0 m/s air flow or still air) with the heat sink depicted in figure 3 on page 7, of di mensions 50 mm x 50 mm x 28 mm (respectively l x l x h). the global junction to ambient thermal resistance rth ja is: 4.8 c/w rth jc + 2.0 c/w thermal grease resistance + 4.0 c/w rth ca (case to ambi- ent) = 10.8 c/w total (rth ja ). assuming: a typical thermal resistance from the junction to the top of the case rth jc of 4.8 c/w (finite element method thermal simulation results): this valu e does not include the thermal contact resistance between the package and the external heat sink (glue, paste, or ther- mal foil interface, for example). as an example, use a 2.0 c/w value for a 50 m thickness of thermal grease. note: example of the calculation of the ambient temperature t a max to ensure t j max = 110 c: assuming rth ja = 10.8 c/w and power dissipation = 4.6 w, t a max = t j - (rth ja x 4.6 w) = 110 - (10.8 x 4.6) = 60.32 c. t a max can be increased by lowering rth ja with an adequate air flow ( 2 m/s, for example).
7 TS83102G0BMGS 5360as?bdc?0 8 /04 figure 3. black anodized aluminium heat sink glued on a copper base screwed on board (all dimensions in mm) note: the cooling system efficiency can be monitored using th e temperature sensing diodes integrated in the device. thermal dissipation by conduction only when the external heat sink cannot be used, the relevant thermal resistance is the thermal resistance from the junction to the bottom of the columns: rth j-bottom-of-columns . the thermal path, in this case, is the junction, then the silicon, glue, cu w heat spreader, pack- age al2o3, and the columns (sn10pb90). the finite element method (fem) with the thermal simulator leads to rth j-bottom-of-columns = 7.4c/w. this value assumes pure conduction from the junction to the bottom of the columns (this is the worst case, no radiation and no convection is applied). with such an assumption, rth j- bottom-of-columns is user-independent. to complete the thermal analysis, you must add the thermal resistance from the top of the board (on which the device is soldered) to the ambient resistance, whose values are user- dependent (the type of board, thermal, routing, area covered by copper in each board layer, thickness, airflow or cold plate are all parameters to consider). in the case of the ci-cga 152 package, the thermal resistance from the junction to the top of the package (via the cuw heat spreader covered by ai203) is rth j-top-of-package = 4.8 c/w. 16 x 50 11.5 x 52 ? 18.50 6.5 board 0.3 2 50 x 50 50 x 52
8 TS83102G0BMGS 5360as?bdc?0 8 /04 figure 4. thermal net silicon junction 2.61 1.7 ?c/watt bottom view bottom of 44 internal columns assumptions: die 3.75x3.84=14.4 mm2 50 m thick epoxy/ag glue pb90sn 10 columns diameter 0.86 mm 2.1 mm l ength under bo ttom of lga 21x21 mm clga 18.5x18.5 mm cuw on top ?c/watt ?c/watt 0.56 2.05 bottom of 52 "between" columns bottom of 56 external columns ?c/watt ?c/watt 0.9 0.5 ?c/watt ?c/watt 0.47 1.75 0.6 ?c/watt ?c/watt ?c/watt 0.44 1.60 silicon junction ceramic package ceramic columns pbsn = 0.40 w/cm/?c = 2.3 w/cm/?c = 0.17 w/cm/?c silicon die 14.4 mm2 cuw heatspreader cuw heatspreader = 0.95 w/cm/?c epoxy/ag glue = 0.02 w/cm/?c = 2.3 w/cm/?c 0.25 ?c/watt 0.25 ?c/watt 3.0 ?c/watt 0.80 ?c/watt to external heatsink if any silicon junction 1.7 infinite heatsink at bottom of columns 0.9 2.04 0.5 2.22 0.6 infinite heatsink at bottom of columns 7.4 ?c/watt (result using spice, thermal to electrical equivalent model) reduction case where all bottoms of columns are connected to infinite heat sink at bottom and no external heatsink on top 0.25 3.0 0.80
9 TS83102G0BMGS 5360as?bdc?0 8 /04 package description hermetic ci-cga 152 outline dimensions figure 5. mechanical description bottom view ceramic body size : 21 x 21 mm column pitch : 1.27 mm cofired : al2o3 package chamfer 0.4 (x4) sci chamfer 1.8 (x4) 16 note: cuw heat spreader on opposite side of package pin a1 index (no column) pb90sn10 columns 152 x o d = 0.89 +/- 0.10 mm 21.00 mm +/- 0.20 0.30 o t ao bo a 21.00 mm +/- 0.20 b 1.27 mm pitch
10 TS83102G0BMGS 5360as?bdc?0 8 /04 figure 6. package top view nickel gold finishing that defines the external heat sink footprint location (electrically isolated from cuw) top surface is ai203 ceramic cuw vertical side is apparent at peripheral under ai203 metalized area for cuw brazing cuw 18.5 mm sq. is brazed on 20.3 mm sq. metalization. ni-au plating cuw side is electrically connected to vee pin a1 index (no column) chamfer 0.5 (x4) 21.00 +/- 0.20 mm sq 18.50 +/- 0.18 mm sq r 7.00 mm r 6.70 mm
11 TS83102G0BMGS 5360as?bdc?0 8 /04 figure 7. cross section cuw heat spreader ai203 plate brazed on cuw this side has no metalization all units in mm combo lid soldered 9.27 mm sq 0.254 mm thick 4.42 +/- 0.40 0.80 +/- 0.09 (0.300) (0.150) 1.62 +/- 0.075 (0.30 +/- 0.05) 1.55 +/- 0.16 0.89 mm +/- 0.10 1.27 mm pitch high t o solder coloumns (pb90sn10) 152 columns in 3 external rows minus 4 corners (0.500) 21.00 +/- 0.20 18.50 +/- 0.13 maximum protrusion 0.20 nominal is 0 0.25
12 TS83102G0BMGS 5360as?bdc?0 8 /04 ordering information part number package temperature range screening level comments tsx83102g0bgs ci-cga152 ambient prototype please contact your local atmel sales office TS83102G0BMGS ci-cga 152 -40 c < t c ; t j < 125 c standard product tsev83102g0bgl cbga 152 ambient prototype evaluation board (delivered with a heat sink)
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